1. Field of the Invention
The present invention relates to a gate array semiconductor integrated circuit device employing MOS transistors which are formed on a semiconductor layer (SOI (silicon on insulator) substrate) provided on a surface of an insulating layer.
2. Description of the Background Art
A gate array semiconductor integrated circuit device is widely employed as a technique capable of forming an LSI circuit in a short development period. In the gate array semiconductor integrated circuit device, steps (generally called a master step) up to those of forming PMOS and NMOS transistors are previously advanced, and connection of the transistors is varied with the user's order so that desired functions can be implemented through contact and wiring steps (generally called a slice step). Due to the previous preparation of the master step, it is possible to form a semiconductor integrated circuit device in a shorter development period as compared with a general semiconductor integrated circuit device.
FIG. 93 is a top plan view showing the structure of a conventional gate array semiconductor integrated circuit device in a block system. As shown in FIG. 93, input/output buffer regions 4 are arranged to enclose an internal transistor region 3 which is formed by foldedly arranging a portion consisting of a PMOS transistor region 1 and a NMOS transistor region 2 adjacent to each other.
FIG. 94 is a top plan view showing a part 5 of the internal transistor region 3 (it is done up to the master step) in FIG. 93 in an enlarge manner, to illustrate the structure of a basic cell BCP. Referring to FIG. 94, symbols PGP, PSDP and PBDP denote gate electrodes, source/drain electrodes and substrate contact arrangement regions of PMOS transistors respectively. Further, symbols NGP, NSDP and NBDP denote gate electrodes, source/drain electrodes and substrate contact arrangement regions of NMOS transistors respectively. In the figure, marks X show actual contact hole opening portions, and the respective electrodes of the transistors and wiring layers as well as the wiring layers themselves are connected with each other through the portions of the marks X. A portion consisting of one of the gate electrodes PGP and two source/drain electrodes PSDP which are adjacent to the gate electrode PGP forms one PMOS transistor, while a portion consisting of one gate electrode NGP and two source/drain electrodes NSDP which are adjacent to the gate electrode NGP forms one NMOS transistor, respectively. The region BCP which is formed by the PMOS transistor region 1 and the NMOS transistor region 2 is called a basic cell. Such basic cells BCP are repeatedly arranged along a transverse direction 6 (a first direction) while being foldedly arranged along a vertical direction 7 (a second direction), thereby forming the internal transistor region 3 (FIG. 93).
FIGS. 95 and 96 are sectional views taken along broken lines AP-BP and CP-DP in FIG. 94 respectively, showing the gate array semiconductor integrated circuit device in the case of employing a bulk silicon substrate 8. Referring to FIGS. 95 and 96, the first letters N and P of respective symbols indicate N-type and P-type semiconductors respectively, while a plus symbol + indicates a semiconductor concentration, i.e., an impurity concentration. Regions provided with the plus symbol + have high impurity concentration. When wiring layers and semiconductor layers are connected with each other, the semiconductor layers corresponding to the connecting regions are increased in concentration.
Referring to FIG. 96, symbols NCP and PCP denote channel regions of NMOS and PMOS transistors respectively the NMOS and PMOS transistors are structured on P and N wells 9 and 10 which are formed on a major surface of the bulk silicon substrate 8 respectively. The PMOS transistors are isolated from the NMOS transistors by field oxide films FOP, while the PMOS transistors themselves and the NMOS transistors themselves are also isolated from each other by field oxide films FOP. The field oxide films FOP isolating the PMOS transistors themselves and the NMOS transistors themselves from each other are so opened that N+ and P+ substrate contact arrangement regions PBDP and NBDP are formed from bottom surfaces of the respective openings toward the interior of the corresponding N and P wells 10 and 9. When voltages are applied to the N+ and P+ substrate contact arrangement regions PBDP and NBDP, potentials of channel regions PCP (N-type semiconductors) of the PMOS transistors and those of channel regions NCP (P-type semiconductors) of the NMOS transistors are fixed at the applied voltages through the N and P wells 10 and 9 respectively.
FIG. 97 is a top plan view showing such an example that a slice cell (also called a macro cell) of a CMOS invertor circuit shown in FIG. 98 as an example is arranged on a master (processed up to the master step). As shown in FIG. 97, the N+ contact arrangement region PBDP (FIG. 96) of the PMOS transistor is connected to a wiring layer 12 having a first source potential through a contact 11, whereby the channel regions PCP (FIG. 96) of the PMOS transistors are biased at the first source potential. On the other hand, the P+ substrate contact arrangement region NBDP (FIG. 96) of the NMOS transistor is connected to a wiring layer 13 having a second source potential through the contact 11, whereby the channel regions NCP of the NMOS transistors are biased at the second source potential.
The PMOS transistors are isolated from each other by connecting adjacent gate electrodes to the wiring layer 12 having the first source potential through contacts, while the adjacent PMOS and NMOS transistors are isolated from the each other by connecting adjacent gate electrodes to the wiring layer 13 having the second source potential through the contacts, although such structures are not shown in FIG. 97. In the gate array semiconductor integrated circuit device, several hundred types of such macro cells are generally prepared, to be capable of coping with various semiconductor integrated devices.
On the other hand, MOS transistors which are formed on the surface of a semiconductor layer (SOl (silicon on insulator) substrate) provided on the surface of a buried oxide film (insulating layer) are noted as new devices since the same can implement low power consumption operations at a high speed with parasitic capacitances which are smaller than those of the MOS transistors formed on the ordinary bulk silicon substrate shown in FIGS. 95 and 96. However, the MOS transistors which are formed on the SOI substrate have such problems that withstand voltages across source/drain electrodes are reduced as compared with those formed on the bulk silicon substrate due to a substrate floating effect of the SOI layers serving as channels of the transistors.
FIG. 99 is a sectional view schematically showing the mechanism of the aforementioned substrate floating effect as to an NMOS transistor, for example. Holes 15 which are generated by impact ionization in the vicinity of a drain electrode 14 are stored in a channel region 17 under a gate electrode 16, to increase the potential of the channel region 17. This induces injection of electrons 19 from a source electrode 18. The electrons 19 injected through the induction reach the vicinity of the drain electrode 14, to newly generate holes 15. Thus, a feedforward loop which is formed by the injection of the electrons 19 and the generation of the holes 15 serves as a factor reducing the withstand voltage across the source/drain electrodes 14 and 18.
In the case of a PMOS transistor, on the other hand, electrons are stored in the channel region to reduce its potential, to deteriorate the withstand voltage of the PMOS transistor, similarly to the above.
Such deterioration of the withstand voltage is severer in the NMOS transistor storing holes, to dominantly influence on deterioration of the withstand voltage of the semiconductor integrated circuit device.
FIGS. 100 and 101 show source-to-drain electrode potential Vds-source-to-drain electrode current Ids characteristics of MOS transistors which are formed on bulk silicon and SOI substrates respectively.
In the case of the MOS transistor which is formed on an SOI substrate, withstand voltages VB1, VB2 and VB3, corresponding to the voltage Vds which is attained when the current Ids is abruptly increased with respect to the source-to-drain electrode voltage Vds, are reduced due to the aforementioned substrate floating effect and, as the result, the source-to-drain electrode current Ids is abruptly increased when the voltage Vds applied across the source/drain electrodes is increased as shown in FIG. 101.
One of methods of preventing the substrate floating effect is that of preventing storage of holes and electrons by fixing the potentials of the channel regions. When this method is applied to the case of driving an integrated circuit device between a first power source and a ground (GND), the channel regions of NMOS and PMOS transistors are fixed at the ground potential and the first source potential respectively, whereby stored holes and electrodes are extracted toward the ground and the first power source respectively.
When the structure (FIGS. 95 and 96) of the conventional gate array semiconductor integrated circuit device which is formed on a bulk silicon substrate is formed on a surface of a buried oxide film 20 as such as shown in FIG. 102 illustrating a conventional gate array which is formed on an SOI substrate as a sectional view taken along the broken line CP-DP in FIG. 94, however, substrate contact arrangement regions PBDP and NBDP and transistor channel regions PCP and NCP are inevitably isolated from each other due to the presence of the buried oxide film 20, and hence the potentials of the channel regions PCP and NCP cannot be fixed. Thus, the aforementioned solving method cannot be implemented.
In order to solve this problem, there has been proposed a method of drawing out an SOI layer from lower portions of gate electrodes PGP and NGP toward substrate contact arrangement regions PBDP and NBDP as shown in FIG. 103, which is drawn as a sectional view taken along the broken line CP-DP in FIG. 94, to thereby fix the potentials of the channel regions PCP, NCP (International Electron Devices Meeting, 1993, 18.5.1-18.5.4, pp. 47-5.478). When this method is applied to the case of driving an integrated circuit device between the first power source and the ground (GND), for example, field shielding gate electrodes FGP are provided as to a PMOS transistor region 1 in a certain basic cell BCP (FIG. 94) and a PMOS transistor region 1 which is adjacent thereto and in relation to an NMOS transistor region 2 in the basic cell BCP and an NMOS transistor region 2 which is adjacent thereto, thereby drawing out respective channel regions PCP and NCP toward substrate contact arrangement regions PBDP and NBDP and forming N-type and P-type regions 21 and 22. Due to the presence of the regions 21 and 22, the channel regions PCP and NCP of PMOS and NMOS transistors are fixed at the first source potential and the ground potential respectively. The field shielding gate electrodes FGP of the PMOS transistor regions are connected to the first power source so that the source/drain electrodes of the PMOS transistors will not conduct through N-type semiconductor layers provided just under the field shielding gate electrodes FGP, while the field shielding gate electrodes FGP of the NMOS transistor regions are connected to the ground so that the source/drain electrodes of the NMOS transistors will not conduct through P-type semiconductor layers provided just under the field shielding gate electrodes FGP. Thus, it is possible to suppress the substrate floating effect, thereby improving the withstand voltage.
In the master structure of the gate array shown in FIG. 103, however, the withstand voltage is disadvantageously reduced when the gate width WP (see FIG. 94) of each transistor is set at a large level. Namely, the gate width WP and the withstand voltage VB are in relation shown in FIG. 104. Even if the potentials of the channel regions are fixed to improve the withstand voltage by the structure shown in FIG. 103, therefore, the withstand voltage may be reduced depending on setting of a desired gate width. Thus, the design range for the gate width is inevitably limited.
Further, the channel regions of the PMOS and NMOS transistors are connected to the first power source and the ground respectively and hence threshold voltages of the transistors turned "on" are at high values by a back gate effect. Thus, the conventional gate array cannot be applied to a semiconductor integrated circuit device which operates at a higher speed.
In the prior art shown in FIG. 103, further, the two techniques of the field shielding gate electrodes FGP and the field oxide films FOP are employed for isolating the transistors from each other, and hence the fabrication process is complicated, leading to increase in cost.